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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC16F883-E/SO. 데이터시트(PDF) 330 Page - Microchip Technology |
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PIC16F883-E/SO. 데이터시트(HTML) 330 Page - Microchip Technology |
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330 / 338 page  PIC16F882/883/884/886/887 DS41291G-page 330 2006-2012 Microchip Technology Inc. STATUS ...................................................................... 31 T1CON ........................................................................ 84 T2CON ........................................................................ 88 TRISA (Tri-State PORTA) ........................................... 41 TRISB (Tri-State PORTB) ........................................... 50 TRISC (Tri-State PORTC) .......................................... 55 TRISD (Tri-State PORTD) .......................................... 59 TRISE (Tri-State PORTE) ........................................... 61 TXSTA (Transmit Status and Control) ...................... 164 VRCON (Voltage Reference Control) ....................... 102 WDTCON (Watchdog Timer Control)........................ 229 WPUB (Weak Pull-up PORTB) ................................... 51 Reset................................................................................. 216 Revision History ................................................................ 323 S SCK................................................................................... 187 SDI .................................................................................... 187 SDO .................................................................................. 187 Serial Clock, SCK.............................................................. 187 Serial Data In, SDI ............................................................ 187 Serial Data Out, SDO........................................................ 187 Serial Peripheral Interface. See SPI Shoot-through Current ...................................................... 148 Slave Mode General Call Address Sequence................... 196 Slave Select Synchronization............................................ 190 Slave Select, SS ............................................................... 187 Sleep ................................................................................. 230 Wake-up.................................................................... 230 Wake-up Using Interrupts ......................................... 230 Software Simulator (MPLAB SIM)..................................... 247 SPBRG.............................................................................. 167 SPBRGH ........................................................................... 167 Special Event Trigger........................................................ 106 Special Function Registers ................................................. 24 SPI Master Mode ............................................................. 189 Serial Clock............................................................... 187 Serial Data In ............................................................ 187 Serial Data Out ......................................................... 187 Slave Select .............................................................. 187 SPI clock ................................................................... 189 SPI Mode .................................................................. 187 SPI Bus Modes ................................................................. 192 SPI Mode Associated Registers with SPI Operation ................. 192 Bus Mode Compatibility ............................................ 192 Effects of a Reset...................................................... 192 Enabling SPI I/O ....................................................... 188 Operation .................................................................. 187 Sleep Operation ........................................................ 192 SPI Module Slave Mode ............................................................... 190 Slave Select Synchronization ................................... 190 Slave Synchronization Timing................................... 190 Slave Timing with CKE = 0 ....................................... 191 Slave Timing with CKE = 1 ....................................... 191 SRCON Register................................................................. 98 SS ..................................................................................... 187 SSP SSPBUF.................................................................... 189 SSPSR...................................................................... 189 SSPCON Register............................................................. 185 SSPCON2 Register........................................................... 186 SSPMSK Register............................................................. 212 SSPOV.............................................................................. 202 SSPOV Status Flag .......................................................... 202 SSPSTAT Register ........................................................... 184 R/W Bit ..................................................................... 194 STATUS Register ............................................................... 31 T T1CON Register ................................................................. 84 T2CON Register ................................................................. 88 Thermal Considerations.................................................... 257 Time-out Sequence .......................................................... 219 Timer0................................................................................. 77 Associated Registers .................................................. 79 External Clock............................................................. 78 Interrupt ...................................................................... 79 Operation .............................................................. 77, 81 Specifications ........................................................... 264 T0CKI ......................................................................... 78 Timer1................................................................................. 81 Associated Registers .................................................. 85 Asynchronous Counter Mode ..................................... 82 Reading and Writing ........................................... 82 Interrupt ...................................................................... 83 Modes of Operation .................................................... 81 Operation During Sleep .............................................. 83 Oscillator..................................................................... 82 Prescaler .................................................................... 82 Specifications ........................................................... 264 Timer1 Gate Inverting Gate ..................................................... 82 Selecting Source .......................................... 82, 96 SR Latch............................................................. 97 Synchronizing COUT w/Timer1 .......................... 96 TMR1H Register ......................................................... 81 TMR1L Register.......................................................... 81 Timer2 Associated Registers .................................................. 88 Timers Timer1 T1CON ............................................................... 84 Timer2 T2CON ............................................................... 88 Timing Diagrams A/D Conversion......................................................... 269 A/D Conversion (Sleep Mode) .................................. 269 Acknowledge Sequence Timing ............................... 205 Asynchronous Reception.......................................... 162 Asynchronous Transmission..................................... 158 Asynchronous Transmission (Back to Back) ............ 159 Auto Wake-up Bit (WUE) During Normal Operation . 172 Auto Wake-up Bit (WUE) During Sleep .................... 173 Automatic Baud Rate Calibration.............................. 171 Baud Rate Generator with Clock Arbitration............. 199 BRG Reset Due to SDA Arbitration .......................... 209 Brown-out Reset (BOR)............................................ 262 Brown-out Reset Situations ...................................... 218 Bus Collision Start Condition Timing ...................................... 208 Bus Collision During a Repeated Start Condition (Case 1)............................................ 210 Bus Collision During a Repeated Start Condition (Case2)............................................. 210 Bus Collision During a Start Condition (SCL = 0) ..... 209 Bus Collision During a Stop Condition...................... 211 Bus Collision for Transmit and Acknowledge ........... 207 CLKOUT and I/O ...................................................... 261 Clock Timing............................................................. 259 |
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