PIC16F883-ESLASHSO. datasheet(331/338 Pages) MICROCHIP

331 / 338 page

 2006-2012 Microchip Technology Inc.

DS41291G-page 331

PIC16F882/883/884/886/887

Comparator Output ..................................................... 89

Enhanced Capture/Compare/PWM (ECCP) ............. 265

EUSART Synchronous Receive (Master/Slave) ....... 270

EUSART Synchronous Transmission

(Master/Slave) .................................................. 270

Fail-Safe Clock Monitor (FSCM) ................................. 76

Full-Bridge PWM Output ........................................... 141

Half-Bridge PWM Output .................................. 139, 148

I2C Bus Data ............................................................. 274

I2C Bus Start/Stop Bits.............................................. 273

I2C Master Mode First Start Bit Timing ..................... 200

I2C Master Mode Reception Timing.......................... 204

I2C Master Mode Transmission Timing..................... 203

I2C Module

Bus Collision

Transmit Timing ........................................ 207

INT Pin Interrupt........................................................ 226

Internal Oscillator Switch Timing................................. 72

Master Mode Transmit Clock Arbitration................... 206

PWM Auto-shutdown

Auto-restart Enabled......................................... 147

Firmware Restart .............................................. 147

PWM Direction Change ............................................ 142

PWM Direction Change at Near 100% Duty Cycle ... 143

PWM Output (Active-High)........................................ 137

PWM Output (Active-Low) ........................................ 138

Repeat Start Condition.............................................. 201

Reset, WDT, OST and Power-up Timer ................... 262

Send Break Character Sequence ............................. 174

Slave Synchronization .............................................. 190

SPI Master Mode (CKE = 1, SMP = 1) ..................... 271

SPI Mode Timing (Master Mode) SPI Mode

Master Mode Timing Diagram .......................... 189

SPI Mode Timing (Slave Mode with CKE = 0) .......... 191

SPI Mode Timing (Slave Mode with CKE = 1) .......... 191

SPI Slave Mode (CKE = 0) ....................................... 272

SPI Slave Mode (CKE = 1) ....................................... 272

Stop Condition Receive or Transmit ......................... 206

Synchronous Reception (Master Mode, SREN) ....... 178

Synchronous Transmission....................................... 176

Synchronous Transmission (Through TXEN) ........... 176

Time-out Sequence

Case 1 .............................................................. 220

Case 2 .............................................................. 220

Case 3 .............................................................. 220

Timer0 and Timer1 External Clock ........................... 264

Timer1 Incrementing Edge.......................................... 83

Two Speed Start-up .................................................... 74

Wake-up from Interrupt ............................................. 231

Timing Parameter Symbology........................................... 258

Timing Requirements

I2C Bus Data ............................................................. 275

I2C Bus Start/Stop Bits ............................................. 274

SPI Mode .................................................................. 273

TRISA ................................................................................. 41

TRISA Register ................................................................... 41

TRISB ................................................................................. 49

TRISB Register ................................................................... 50

TRISC ................................................................................. 55

TRISC Register................................................................... 55

TRISD ................................................................................. 59

TRISD Register................................................................... 59

TRISE ................................................................................. 61

TRISE Register ................................................................... 61

Two-Speed Clock Start-up Mode ........................................ 73

TXREG ............................................................................. 157

TXSTA Register................................................................ 164

BRGH Bit .................................................................. 167

Ultra Low-Power Wake-up................................ 18, 20, 42, 43

Voltage Reference (VR)

Specifications ........................................................... 266

Voltage Reference. See Comparator Voltage

Reference (CVREF)

Voltage References

Associated Registers................................................ 102

VP6 Stabilization ........................................................ 99

VREF. SEE ADC Reference Voltage

Wake-up on Break ............................................................ 172

Wake-up Using Interrupts ................................................. 230

Watchdog Timer (WDT).................................................... 228

Associated Registers................................................ 229

Clock Source ............................................................ 228

Modes....................................................................... 228

Period ....................................................................... 228

Specifications ........................................................... 263

Waveform for Slave Mode General Call Address

Sequence ................................................................. 196

WCOL............................................................... 200, 202, 205

WCOL Status Flag............................................ 200, 202, 205

WDTCON Register ........................................................... 229

WPUB Register................................................................... 51

WWW Address ................................................................. 333

WWW, On-Line Support ..................................................... 13

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