PIC16F883-ESLASHSO. datasheet(115/338 Pages) MICROCHIP

115 / 338 page

 2006-2012 Microchip Technology Inc.

DS41291G-page 115

PIC16F882/883/884/886/887

10.0 DATA EEPROM AND FLASH

PROGRAM MEMORY

CONTROL

The Data EEPROM and Flash program memory are

readable and writable during normal operation (full VDD

range). These memories are not directly mapped in the

addressed through the Special Function Registers

(SFRs). There are six SFRs used to access these

memories:

• EECON1

• EECON2

• EEDAT

•EEDATH

• EEADR

• EEADRH (bit 4 on PIC16F886/PIC16F887 only)

When interfacing the data memory block, EEDAT holds

the 8-bit data for read/write, and EEADR holds the

address of the EEDAT location being accessed. These

devices have 256 bytes of data EEPROM with an

address range from 0h to 0FFh.

When accessing the program memory block of the

PIC16F886/PIC16F887 devices, the EEDAT and EED-

ATH registers form a 2-byte word that holds the 14-bit

data for read/write, and the EEADR and EEADRH reg-

isters form a 2-byte word that holds the 12-bit address

of the EEPROM location being read. The PIC16F882

devices have 2K words of program EEPROM with an

address range from 0h to 07FFh. The PIC16F883/

PIC16F884 devices have 4K words of program

EEPROM with an address range from 0h to 0FFFh.

The program memory allows one-word reads.

The EEPROM data memory allows byte read and write.

A byte write automatically erases the location and

writes the new data (erase before write).

The write time is controlled by an on-chip timer. The

write/erase voltages are generated by an on-chip

charge pump rated to operate over the voltage range of

the device for byte or word operations.

Depending on the setting of the Flash Program

Memory Self Write Enable bits WRT<1:0> of the

Configuration Word Register 2, the device may or may

not be able to write certain blocks of the program

memory. However, reads from the program memory

are allowed.

When the device is code-protected, the CPU may

continue to read and write the data EEPROM memory

and Flash program memory. When code-protected, the

device programmer can no longer access data or

program memory.

10.1

EEADR and EEADRH Registers

The EEADR and EEADRH registers can address up to

a maximum of 256 bytes of data EEPROM or up to a

maximum of 8K words of program EEPROM.

When selecting a program address value, the MSB of

the address is written to the EEADRH register and the

LSB is written to the EEADR register. When selecting a

data address value, only the LSB of the address is

written to the EEADR register.

10.1.1

EECON1 AND EECON2 REGISTERS

EECON1 is the control register for EE memory

accesses.

Control bit EEPGD determines if the access will be a pro-

gram or data memory access. When clear, as it is when

reset, any subsequent operations will operate on the data

memory. When set, any subsequent operations will oper-

ate on the program memory. Program memory can only

be read.

Control bits RD and WR initiate read and write,

respectively. These bits cannot be cleared, only set, in

software. They are cleared in hardware at completion

of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature

termination of a write operation.

The WREN bit, when set, will allow a write operation to

data EEPROM. On power-up, the WREN bit is clear.

The WRERR bit is set when a write operation is

interrupted by a MCLR or a WDT Time-out Reset

during normal operation. In these situations, following

Reset, the user can check the WRERR bit and rewrite

the location.

Interrupt flag bit EEIF of the PIR2 register is set when

write is complete. It must be cleared in the software.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the data EEPROM write sequence.

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