PIC16F883-ESLASHSO. datasheet(121/338 Pages) MICROCHIP

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DS41291G-page 121

PIC16F882/883/884/886/887

10.2

Writing to Flash Program Memory

Flash program memory may only be written to if the

destination address is in a segment of memory that is

not write-protected, as defined in bits WRT<1:0> of the

Configuration Word Register 2. Flash program memory

must be written in eight-word blocks (four-word blocks

for 4K memory devices). See Figures 10-2 and 10-3 for

more details. A block consists of eight words with

sequential addresses, with a lower boundary defined

by an address, where EEADR<2:0> = 000. All block

writes to program memory are done as 16-word erase

by eight-word write operations. The write operation is

edge-aligned and cannot occur across boundaries.

To write program data, it must first be loaded into the

buffer registers (see Figure 10-2). This is accomplished

by first writing the destination address to EEADR and

EEADRH and then writing the data to EEDATA and

EEDATH. After the address and data have been set up,

then the following sequence of events must be

executed:

Set the EEPGD control bit of the EECON1

Write 55h, then AAh, to EECON2 (Flash

programming sequence).

Set the WR control bit of the EECON1 register.

All eight buffer register locations should be written to

with correct data. If less than eight words are being

written to in the block of eight words, then a read from

the program memory location(s) not being written to

must be performed. This takes the data from the pro-

gram location(s) not being written and loads it into the

EEDATA and EEDATH registers. Then the sequence of

events to transfer data to the buffer registers must be

executed.

To transfer data from the buffer registers to the program

memory, the EEADR and EEADRH must point to the last

location in the eight-word block (EEADR<2:0> = 111).

Then the following sequence of events must be

executed:

Set the EEPGD control bit of the EECON1

Write 55h, then AAh, to EECON2 (Flash

programming sequence).

Set control bit WR of the EECON1 register to

begin the write operation.

The user must follow the same specific sequence to

initiate the write for each word in the program block,

writing each program word in sequence (000, 001,

010, 011, 100, 101, 110, 111). When the write is

performed on the last word (EEADR<2:0> = 111), a

block of sixteen words is automatically erased and the

content of the eight word buffer registers are written

into the program memory.

After the “BSF EECON1,WR” instruction, the processor

requires two cycles to set up the erase/write operation.

The user must place two NOP instructions after the WR

bit is set. Since data is being written to buffer registers,

the writing of the first seven words of the block appears

to occur immediately. The processor will halt internal

operations for the typical 4 ms, only during the cycle in

which the erase takes place (i.e., the last word of the

sixteen-word block erase). This is not Sleep mode as

the clocks and peripherals will continue to run. After the

eight-word write cycle, the processor will resume oper-

ation with the third instruction after the EECON1 write

instruction. The above sequence must be repeated for

the higher eight words.

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