Z8018010VSC datasheet(36/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

Timing Diagrams

Z80180 Timing signals are displayed in Figure 16 through Figure 27.

tSRSI

CSIO Receive Data Set-up Time (Internal Clock

Operation)

1–

tcyc

tSRHI

CSIO Receive Data Hold Time (Internal Clock

Operation)

1–

tcyc

tSRSE

CSIO Receive Data Set-up Time (External Clock

Operation)

1–

tcyc

tSRHE

CSIO Receive Data Hold Time (External Clock

Operation)

1–

tcyc

tRES

RESET Set-up Time to Ø Fall

–

tREH

RESET Hold Time from Ø Fall

–

tOSC

Oscillator Stabilization Time

–

TBD

tEXr

External Clock Rise Time (EXTAL)

–

tEXf

External Clock Fall Time (EXTAL)

–

tRr

RESET Rise Time

–

tRf

RESET Fall Time

–

tIr

Input Rise Time (except EXTAL, RESET)–

100

tIf

Input Fall Time (except EXTAL, RESET)–

100

Table 9. Z80180-10 AC Characteristics (continued)

Symbol Item

Z80180-10

Unit

Min

Max

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