T0076-01

PFDPulse

WidthDelay

PFDPulse

WidthDelay

0V

V

CC

PRI_REForSEC_REF

ClockFedThroughthe

MDividerandDelay

VCXO_INClockFedThrough

theNDividerandDelay

CP_DIR(Bit2ofWord2=0,

DefaultState)

CP_DIR(Bit2ofWord2=1)

V

(InternalSignal)

(PFD1)

V

(InternalSignal)

(PFD2)

CDCM7005

www.ti.com

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

Charge Pump Preset to VCC_CP/2

The preset charge pump to VCC_CP/2 is a useful feature to quickly set the center frequency of the VC(X)O after

powerup or reset. The adequate control voltage for the VC(X)O will be provided to the charge-pump output by an

internal voltage divider of 1 k

Ω/1 kΩ to VCC_CP and GND (VCC_CP/2).

This feature helps to get the initial frequency accuracy, i.e. required at CPRI (Common Public Radio Interface) or

OBSAI (Open Base Station Architecture Initiative).

The preset charge pump to VCC_CP/2 can be set and reset by SPI register (word 2, bit 3). This feature must be

disabled for PLL locking.

Charge Pump Current Direction

The direction of the charge pump (CP) current pulse can be changed by the SPI register (word 2, bit 2). It

determines in which direction the CP current regulates (reference clock leads to feedback clock). Most

applications use the positive CP output current (power-up condition) because of the use of a passive loop filter.

The negative CP current is useful when using an active loop filter concept with inverting operational amplifier.

Figure 23 shows the internal PFD signal and the corresponding CP current.

NOTE: The purpose of the PFD pluse width delay is to improve spurious suppression.

Figure 23. Charge Pump Current Direction (VCXO and VCO Support)

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