CDCM7005_13 datasheet(36/45 Pages) TI

36 / 45 page

CDCM7005

SCAS793E – JUNE 2005 – REVISED FEBRUARY 2013

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Changes from Revision C (December 2007) to Revision D

Page

•

Changed VCC pin text From: 3.3-V supply. There is no internal connection between VCC and AVCC. It is

recommended that AVCC use its own supply filter. To: 3.3-V supply. VCC and AVCC should always have the same

supply voltage. It is recommended that AVCC use its own supply filter. ............................................................................... 4

•

Added text to the CTRL_LE pin - Unused or floating inputs must be tied to proper logic level. A 20k

Ω or larger

pull

−up resistor to VCC is recommended. ............................................................................................................................ 4

•

Added text to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. A 20k

Ω or larger

pull

−up resistor to VCC is recommended. ............................................................................................................................ 4

•

Added text to the CTRL_DATA pin - Unused or floating inputs must be tied to proper logic level. A 20k

Ω or larger

pull

−up resistor to VCC is recommended. ............................................................................................................................ 4

•

Added text to the PD pin - It is recommended to ramp up the PD with the same time as VCC and AVCC or later. The

ramp up rate of the PD should not be faster than the ramp up rate of VCC and AVCC. ........................................................ 4

•

Added text to the SPI CONTROL INTERFACE section - Unused or floating inputs must be tied to proper logic level.

A 20k

Ω or larger pull−up resistor to VCC is recommended. .............................................................................................. 17

•

Added text to the SPI CONTROL INTERFACE section - It is recommended to program Word 0, Word 1, Word 2

and Word 3 right after power up and PD becomes HIGH. ................................................................................................. 17

•

Changed From: RES To: GTME ......................................................................................................................................... 21

•

Changed From: RES To: PFDFC ....................................................................................................................................... 21

Changes from Revision D (August 2009) to Revision E

Page

•

Changed PLL_LOCK pin description, replaced cycle-slip text. ............................................................................................ 5

•

Changed Note 1 of table Word 3 ........................................................................................................................................ 21

•

Changed table Word 3, Cycle Slip (Bit 6) To: Frequency Offset ........................................................................................ 21

•

Changed table Lock-Detect Window (Word 3) - Clip slip To: Frequency offset, and Note 2 ............................................. 23

•

Changed the Frequency Hold-Over Mode section ............................................................................................................. 29

•

Changed text From: Cycle-Slip To: Frequency Offset in Figure 22 .................................................................................... 30

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