UVLO

3

RON

4

RTN

1

VIN

2

8

SW

7

BST

6

VCC

5

FB

SO

PowerPAD-

8

Exp Pad

SW

BST

VCC

FB

8

7

6

5

1

2

3

4

UVLO

RON

RTN

VIN

WSON-8

Exp Pad

LM5017

SNVS783D – JANUARY 2012 – REVISED MAY 2013

www.ti.com

Connection Diagram

Figure 1. Top View (Connect Exposed Pad to RTN)

Figure 2. Top View (Connect Exposed Pad to RTN)

Pin Descriptions

Pin

Name

Description

Application Information

1

RTN

Ground

Ground connection of the integrated circuit.

2

Input Voltage

Operating input range is 9V to 100V.

3

UVLO

Input Pin of Undervoltage Comparator

undervoltage detection threshold. An internal current

source is enabled when UVLO is above 1.225V to

provide hysteresis. When UVLO pin is pulled below

0.66V externally, the parts goes in shutdown mode.

4

On-Time Control

time is 100ns at max input voltage.

5

FB

Feedback

This pin is connected to the inverting input of the internal

regulation comparator. The regulation level is 1.225V.

6

Output from the Internal High Voltage Series Pass

Regulator. Regulated at 7.6V

gate drivers and other internal circuitry. A 1.0

μF

decoupling capacitor is recommended.

7

BST

Bootstrap Capacitor

An external capacitor is required between the BST and

SW pins (0.01

μF ceramic). The BST pin capacitor is

when the SW pin is low.

8

SW

Switching Node

Power switching node. Connect to the output inductor

and bootstrap capacitor.

EP

Exposed Pad

Exposed pad must be connected to RTN pin. Connect to

system ground plane on application board for reduced

thermal resistance.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

2

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