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MMPF0100NPEP 데이터시트(PDF) 100 Page - Freescale Semiconductor, Inc |
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MMPF0100NPEP 데이터시트(HTML) 100 Page - Freescale Semiconductor, Inc |
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100 / 137 page ![]() Analog Integrated Circuit Device Data 100 Freescale Semiconductor PF0100 Functional Block Requirements and Behaviors Power Generation Figure 26. VSNVS Supply Switch Architecture Table 106 provides a summary of the VSNVS operation at different input voltage VIN and with or without coin cell connected to the system. VSNVS Control The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 107. VSNVS External Components Table 106. VSNVS Modes of Operation VSNVSVOLT[2:0] VIN MODE 110 > VTH1 VIN LDO 3.0 V 110 < VTL1 Coin cell switch 000 – 101 > VTH0 VIN LDO 000 – 101 < VTL0 Coin cell LDO Table 107. Register VSNVSCTL - ADDR 0x6B Name Bit # R/W Default Description VSNVSVOLT 2:0 R/W 0x80 Configures VSNVS output voltage.(68) 000 = 1.0 V 001 = 1.1 V 010 = 1.2 V 011 = 1.3 V 100 = 1.5 V 101 = 1.8 V 110 = 3.0 V 111 = RSVD UNUSED 7:3 – 0x00 UNUSED Notes 68. Only valid when a valid input voltage is present. Table 108. VSNVS External Components Capacitor Value ( F) VSNVS 0.47 LDO\ PF0100 VSNVS Coin Cell 1.8 - 3.3 V VIN 2.25 V (VTL0) - 4.5 V LICELL Charger LDO/SWITCH VREF + _ Z Input Sense/ Selector I 2C Interface |
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