JS28F256P33BFE datasheet(5/90 Pages) MICRON

5 / 90 page

Datasheet

Aug 2009

Order Number:320003-08

P33-65nm

1.0

Functional Description

1.1

Introduction

This document provides information about the NumonyxTM StrataFlash® Embedded

Memory (P33-65nm) device and describes its features, operations, and specifications.

P33-65nm is the latest generation of NumonyxTM StrataFlash® Embedded Memory

(P33-65nm) devices. P33-65nm device will be offered in 64-Mbit up through 2-Gbit

densities. This document covers specifically 256-Mbit and 512-Mbit (256M/256M)

product information. Benefits include more density in less space, high-speed interface

NOR device, and support for code and data storage. Features include high-performance

synchronous-burst read mode, fast asynchronous access times, low power, flexible

security options, and two industry-standard package choices.

P33-65nm is manufactured using Numonyx™ 65nm ETOX™ X process technology.

1.2

Overview

This family of devices provides high performance at low voltage on a 16-bit data bus.

Individually erasable memory blocks are sized for optimum code and data storage.

Upon initial power-up or return from reset, the device defaults to asynchronous page-

mode read. Configuring the RCR enables synchronous burst-mode reads. In

synchronous burst mode, output data is synchronized with a user-supplied clock signal.

A WAIT signal provides an easy CPU-to-flash memory synchronization.

In addition to the enhanced architecture and interface, the device incorporates

technology that enables fast factory program and erase operations. Designed for low-

voltage systems, the P33 Family Flash memory supports read operations with VCC at

3.0V, and erase and program operations with VPP at 3.0V or 9.0V. Buffered Enhanced

Factory Programming provides the fastest flash array programming performance with

VPP at 9.0V, which increases factory throughput. With VPP at 3.0V, VCC and VPP can be

tied together for a simple, ultra low power design. In addition to voltage flexibility, a

dedicated VPP connection provides complete data protection when VPP ≤ VPPLK.

The Command User Interface is the interface between the system processor and all

internal operations of the device. An internal Write State Machine automatically

executes the algorithms and timings necessary for block erase and program. A Status

An industry-standard command sequence invokes program and erase automation. Each

erase operation erases one block. The Erase Suspend feature allows system software to

pause an erase cycle to read or program data in another block. Program Suspend

allows system software to pause programming to read other locations. Data is

programmed in word increments (16 bits).

The P33 Family Flash memory one-time-programmable (OTP) register allows unique

flash device identification that can be used to increase system security. The individual

Block Lock feature provides zero-latency block locking and unlocking. The P33-65nm

device adds enhanced protection via Password Access Mode which allows user to

protect write and/or read access to the defined blocks. In addition, the P33 Family

Flash memory may also provide the backward compatible OTP permanent lock feature.

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