GD82541PI datasheet(17/46 Pages) INTEL

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Networking Silicon — 82541(PI/GI/EI)

3.6

Test Interface Signals (6)

3.7

Power Supply Connections

3.7.1

Digital and Analog Supplies

MDI[3]+/-

Media Dependent Interface [3].

1000BASE-T: In MDI configuration, MDI[3]+/- corresponds to BI_DC+/-, and in MDI-X

configuration, MDI[3]+/- corresponds to BI_DD+/-.

100BASE_TX: Unused.

10BASE-T: Unused.

IEEE_TEST-

IEEE test pin output minus. Used to gain access to the internal PHY clock for

1000BASE-T IEEE physical layer conformance testing.

IEEE_TEST+

Analog test pin output plus. Used to gain access to the internal PHY clock for

1000BASE-T IEEE physical layer conformance testing.

Symbol

Type

Name and Function

TEST

Test Enable. Enables test mode.

Normal mode: connect to VSS.

JTAG_TCK

JTAG Test Access Port Clock.

JTAG_TDI

JTAG Test Access Port Data In.

JTAG_TDO

JTAG Test Access Port Data Out.

JTAG_TMS

JTAG Test Access Port Mode Select.

JTAG_TRST#

JTAG Test Access Port Reset. This is an active low reset signal for JTAG.

To disable the JTAG interface, this signal should be terminated using pull-

down resistor (1 K

Ω for the 82541GI(EI) and 100 Ω for the 82541PI) to

ground. It must not be left unconnected.

Symbol

Type

Name and Function

3.3V

3.3 V I/O Power Supply.

ANALOG_1.8V

1.8 V Analog Power Supply.

CLKR_1.8V

1.8 V analog power supply for the clock recovery.

XTAL_1.8V

Input power for the XTAL regulator.

1.2V

1.2 V Power supply. For analog and digital circuits.

ANALOG_1.2V

1.2 V Analog Power Supply.

PLL_1.2V

Input power for the ICS regulator.

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