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GD82541PI 데이터시트(PDF) 31 Page - Intel Corporation |
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GD82541PI 데이터시트(HTML) 31 Page - Intel Corporation |
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31 / 46 page ![]() Networking Silicon — 82541(PI/GI/EI) 31 NOTE: 50 pF load used for maximum times. Minimum times are specified with 0 pF load. Figure 10. TVAL Test Load (PCI 5 V Signaling Environment) 50 pF Pin Test Point 1/2 inch max. Table 20. Link Interface Rise and Fall Times Symbol Parameter Condition Min Max Unit TR Clock rise time 0.8 V to 2.0 V 0.7 ns TF Clock fall time 2.0 V to 0.8 V 0.7 ns TR Data rise time 0.8 V to 2.0 V 0.7 ns TF Data fall time 2.0 V to 0.8 V 0.7 ns Figure 11. Link Interface Rise/Fall Timing 2.0 V 0.8 V TF TR |
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