GD82541PI datasheet(28/46 Pages) INTEL

부품명	GD82541PI

상세설명	82541 Family of Gigabit Ethernet Controllers

PDF	46 Pages

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제조업체	INTEL [Intel Corporation]

홈페이지	http://www.intel.com

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28 / 46 page

82541(PI/GI/EI) — Networking Silicon

NOTES:

1. Output timing measurements are as shown.

2. REQ# and GNT# signals are point-to-point and have different output valid delay and input setup times than

bussed signals. GNT# has a setup of 10 ns; REQ# has a setup of 12 ns. All other signals are bussed.

3. Input timing measurements are as shown.

Figure 4. AC Test Loads for General Output Pins

Table 18. PCI Bus Interface Timing Parameters

Symbol

Parameter

PCI 66MHz

PCI 33 MHz

Units

MinMax

TVAL

CLK to signal valid delay: bussed

signals

TVAL(ptp)

CLK to signal valid delay: point-

to-point signals

TON

Float to active delay

TOFF

Active to float delay

TSU

Input setup time to CLK: bussed

signals

TSU(ptp)

Input setup time to CLK: point-to-

point signals

10, 12

Input hold time from CLK

0.6 Vcc

0.2 Vcc

0.5 Vcc

0.4 Vcc

0.3 Vcc

Tcyc

0.4 Vcc p-to-p

(minimum)

3.3 V Clock

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