Optoisolated RS232 Interface Application Example

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

Freescale Semiconductor

31

operating conditions, this timeout will cause the Fault state to be automatically exited to the

PWM0RPM state, where motion will once again be initiated if a CmdFwd or CmdRev has been

received. The exceptions to this rule are the cases when the Fault state was entered from the

PWMHighZ or PWMOFF states, in which case, exiting from the Fault state will return back to these

states.

Optoisolated RS232 Interface Application Example

Some motor control systems have the control electronics operating at the same potential as the high

voltage bus. Connecting a PC to that system could present safety issues, due to the high voltage potential

between the motor control system and the PC. Figure 19 is an example of a simple circuit that can be

used with the MC3PHAC to isolate the serial port of the PC from the motor control system.

The circuit in Figure 19 is the schematic of a half-duplex optoisolated RS232 interface. This isolated

terminal interface provides a margin of safety between the motor control system and a personal computer.

The EIA RS232 specification states the signal levels can range from ±3 to ±25 volts. A Mark is defined by

the EIA RS232 specification as a signal that ranges from –3 to –25 volts. A Space is defined as a signal

that ranges from +3 to +25 volts. Therefore, to meet the RS232 specification, signals to and from a

terminal must transition through 0 volts as it changes from a Mark to a Space. Breaking the circuit down

into an input and output section simplifies the explanation of the circuit.

Figure 19. Optoisolated RS232 Circuit

To send data from a PC to the MC3PHAC, it is necessary to satisfy the serial input of the MC3PHAC. In

the idle condition, the serial input of the MC3PHAC must be at a logic 1. To accomplish that, the transistor

in U1 must be turned off. The idle state of the transmit data line (TxD) from the PC serial port is a Mark

(–3 to –25 volts). Therefore, the diode in U1 is off and the transistor in U1 is off, yielding a logic 1 to the

MC3PHAC’s serial input. When the start bit is sent to the MC3PHAC from the PC’s serial port, the PC’s

TxD transitions from a Mark to a Space (+3 to +25 volts), thus forward biasing the diode in U1. Forward

biasing the diode in D1 turns on the transistor in U1, providing a logic 0 to the serial input of the

MC3PHAC. Simply stated, the input half of the circuit provides input isolation, signal inversion, and level

5

9

4

8

3

7

2

6

1

GND

DTR

TxD

RTS

RxD

D3

1N4148

D2

1N4148

R3

4.7 k

Ω

D1

1N4148

R1

1 k

Ω

1

2

+

C1

2.2

µF/50 V

~+12 V

4

5

U1

4N35

U2

4N35

+5 V

TO MC3PHAC PIN 17

4

5

1

2

R4

330

Ω

+5 V

R2

1 k

Ω

TO MC3PHAC PIN 16

ISOLATION BARRIER

RS232 ISOLATED

HALF-DUPLEX, MAXIMUM 9600 BAUD

J1

CON/CANNON9

FEMALE