Features

MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

Freescale Semiconductor

13

logic, and can cause the device to malfunction. The same noise spike applied to the input of a PLL clock

circuit is perceived by the PLL as a change in its reference frequency, and the PLL output frequency

begins to change in an attempt to lock on to the new frequency. However, before any appreciable change

can occur, the spike is gone, and the PLL settles back into the true reference frequency.

Fault Protection — The MC3PHAC supports an elaborate range of fault protection and prevention

features. If a fault does occur, the MC3PHAC immediately disables the PWMs and waits until the fault

condition is cleared before starting a timer to re-enable the PWMs. Refer to the graph in Figure 10 for the

resistance value versus retry time. Figure 10 assumes a 6.8 k

Ω pullup resistor. In standalone mode, this

timeout interval is specified during the initialization phase by supplying a voltage to the MUX_IN pin while

the RETRY_TxD pin is being driven low. In this way, the retry time can be specified from 1 to 60 seconds,

with a scaling factor of 12 seconds per volt. In PC master software mode, the retry time can be specified

from 0.25 second to over 4.5 hours and can be changed at any time.

The fault protection and prevention features are:

•

External Fault Monitoring — The FAULTIN pin accepts a digital signal that indicates a fault has

been detected via external monitoring circuitry. A high level on this input results in the PWMs being

immediately disabled. Typical fault conditions might be a dc bus over voltage, bus over current, or

over temperature. Once this input returns to a logic low level, the fault retry timer begins running,

and PWMs are re-enabled after the programmed timeout value is reached.

•

Lost Clock Protection — If the signal on the OSC1 pin is lost altogether, the MC3PHAC will

immediately disable the PWM outputs to protect the motor and power electronics. This is a special

fault condition in that it will also cause the MC3PHAC to be reset. Lost clock detection is an

important safety consideration, as many safety regulatory agencies are now requiring a dead

crystal test be performed as part of the certification process.

•

reset the MC3PHAC. This allows the MC3PHAC to operate properly with 5 volt power supplies of

either 5 or 10 percent tolerance.

•

Bus Voltage Integrity Monitoring — The DC_BUS pin is monitored at a 5.3 kHz frequency

(4.0 kHz when the PWM frequency is set to 15.9 kHz), and any voltage reading outside of an

acceptable window constitutes a fault condition. In standalone mode, the window thresholds are

fixed at 4.47 volts (128 percent of nominal), and 1.75 volts (50 percent of nominal), where nominal

is defined to be 3.5 volts. In PC master software mode, both top and bottom window thresholds can

be set independently to any value between 0 volts (0 percent of nominal), and greater than 5 volts

(143 percent of nominal), and can be changed at any time. Once the DC_BUS signal level returns

to a value within the acceptable window, the fault retry timer begins running, and PWMs are re-

enabled after the programmed timeout value is reached.

charges up to its nominal value. When the dc bus integrity is checked, an under voltage would be

detected and treated as a fault, with its associated timeout period. To prevent this, the MC3PHAC

monitors the dc bus voltage during power-up in standalone mode, and waits until it is higher than

the under voltage threshold before continuing. During this time, all MC3PHAC functions are

suspended. Once this threshold is reached, the MC3PHAC will continue normally, with any further

under voltage conditions treated as a fault.

If dc bus voltage monitoring is not desired, a voltage of 3.5 volts ± 5 percent should be supplied to

the DC_BUS pin through an impedance of between 4.7 k

Ω and 15 kΩ.