MC3PHAC Monolithic Intelligent Motor Controller, Rev. 2

12

Freescale Semiconductor

Features

illustrated in Figure 6. To compensate for this voltage loss, the voltage profile is boosted over the normal

voltage curve in Figure 5, so that the magnetizing current remains constant over the speed range.

Figure 5. Voltage Profiling, Including Voltage Boost

Figure 6. AC Motor Single Phase Model Showing Parasitic Stator Impedances

The MC3PHAC allows the voltage boost to be specified as a percentage of full voltage at 0 Hz, as shown

in Figure 5. In standalone mode, voltage boost is specified during the initialization phase by supplying

a voltage to the MUX_IN pin while the VBOOST_MODE pin is being driven low. Refer to the graph in

Figure 11 for the resistance value versus voltage boost. Figure 11 assumes a 6.8 k

Ω pullup resistor. In

this way, voltage boost can be specified from 0 to 40 percent, with a scaling factor of 8 percent per volt.

In PC master software mode, the voltage boost can be specified from 0 to 100 percent and can be

changed at anytime.

By using the voltage boost value, and the specified base frequency, the MC3PHAC has all the information

required to generate a voltage profile automatically based on the generated waveform frequency. An

additional feature exists in PC master software mode whereby this voltage value can be overridden and

controlled in real time. Specifying a voltage lower than the normal volts-per-hertz profile permits a softer

torque response in certain ergonomic situations. It also allows for load power factor control and higher

operating efficiencies with high inertia loads or other loads where instantaneous changes in torque

demand are not permitted. Details of this feature are discussed in the PC Master Software Operation with

the MC3PHAC.

PLL Clock Generation — The OSC1 pin signal is used as a reference clock for an internal PLL clocking

circuit, which is used to drive the internal clocks of the MC3PHAC. This provides excellent protection

against noise spikes that may occur on the OSC1 pin. In a clocking circuit that does not incorporate a PLL,

a noise spike on the clock input can create a clock edge, which violates the setup times of the clocking

CO

MP

EN

SA

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OR

ST

AT

OR

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SS

ES

FREQUENCY

BASE FREQUENCY

VOLTAGE BOOST

100%

PARASITICS

MAGNETIZING CURRENT

(TRY TO KEEP CONSTANT)

TORQUE CURRENT

R2 (1 –s)

s