DOC7707 datasheet(47/307 Pages) ETC1

47 / 307 page

7707F–AVR–11/10

AT90USB82/162

Figure 9-1.

Reset Logic

Notes:

1. The POR will not work unless the supply voltage has been below VPOT (falling)

9.3

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in Table 9-1. The POR is activated whenever V

CC is below the detection level. The

POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply

voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

Table 9-1.

Reset Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

VPOT

Power-on Reset Threshold Voltage (rising)

1.4

2.3

Power-on Reset Threshold Voltage (falling)(1)

1.3

2.3

VPOR

VCC Start Voltage to ensure internal Power-on

Reset signal

-0.1

0.1

VCCRR

VCC Rise Rate to ensure internal Power_on

Reset signal

0.8

V/ms

VRST

RESET Pin Threshold Voltage

0.2

Vcc

0.85

Vcc

tRST

Minimum pulse width on RESET Pin

5V, 25°C

400

MCU Status

Brown-out

Reset Circuit

BODLEVEL [2..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

USB Device

Reset Detection

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

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