VMV3 datasheet(27/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-13

Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings 1

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

CLOAD (pF)

VCCI (V)

Static Power

PDC7 (mW)2

Dynamic Power

PAC10 (µW/MHz)3

Single-Ended

3.3 V LVTTL/LVCMOS

3.3

–

148.00

3.3 V LVCMOS Wide Range

3.3

–

148.00

2.5 V LVCMOS

2.5

–

83.23

1.8 V LVCMOS

1.8

–

54.58

1.5 V LVCMOS (JESD8-11)

1.5

–

37.05

1.2 V LVCMOS

1.2

–

17.94

1.2 V LVCMOS Wide Range

1.2

–

17.94

3.3 V PCI

3.3

–

204.61

3.3 V PCI-X

3.3

–

204.61

Voltage-Referenced

3.3 V GTL

3.3

–

24.08

2.5 V GTL

2.5

–

13.52

3.3 V GTL+

3.3

–

24.10

2.5 V GTL+

2.5

–

13.54

HSTL (I)

1.5

7.08

26.22

HSTL (II)

1.5

13.88

27.18

SSTL2 (I)

2.5

16.69

105.56

SSTL2 (II)

2.5

25.91

116.48

SSTL3 (I)

3.3

26.02

114.67

SSTL3 (II)

3.3

42.21

131.69

Differential

LVDS

–

2.5

7.70

89.58

LVPECL

–

3.3

19.42

167.86

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output slew.

2. PDC7 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCCI.

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