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VMV3 데이터시트(PDF) 39 Page - Microsemi Corporation

부품명 VMV3
상세설명  Military ProASIC3/EL Low Power Flash FPGAs with Flash*Freeze Technology
PDF  212 Pages
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제조업체  MICROSEMI [Microsemi Corporation]
홈페이지  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

VMV3 데이터시트(HTML) 39 Page - Microsemi Corporation

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Military ProASIC3/EL Low Power Flash FPGAs
Revision 3
2-25
Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military
Conditions—Software Default Settings
Applicable to Advanced I/O Banks for A3P250 and A3P1000 Only
I/O Standard
Drive
Strength
Equiv.
Software
Default
Drive
Strength
Option1
Slew
Rate
VIL
VIH
VOL
VOH
IOL2 IOH2
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
12 mA
High –0.3
0.8
2
3.6
0.4
2.4
12 12
3.3 V LVCMOS
Wide Range1,3
100 µA
12 mA
High –0.3
0.8
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V LVCMOS 12 mA
12 mA
High –0.3
0.7
1.7
2.7
0.7
1.7
12 12
1.8 V LVCMOS 12 mA
12 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
VCCI – 0.45 12 12
1.5 V LVCMOS 12 mA
12 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12 12
3.3 V PCI
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. Currents are measured at 125°C junction temperature.
3. Output slew rate can be extracted using the IBIS Models.
4. Output drive strength is below JEDEC specification.
5. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Military
Conditions—Software Default Settings
Applicable to Standard Plus I/O Banks for A3P250 and A3P1000 Only
I/O Standard
Drive
Strength
Equiv.
Software
Default
Drive
Strength
Option1
Slew
Rate
VIL
VIH
VOL
VOH
IOL2 IOH2
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
3.3 V LVTTL /
3.3 V LVCMOS
12 mA
12 mA
High –0.3
0.8
2
3.6
0.4
2.4
12
12
3.3 V LVCMOS
Wide Range1,3
100 µA
12 mA
High –0.3
0.8
2
3.6
0.2
VCCI – 0.2 0.1 0.1
2.5 V LVCMOS 12 mA
12 mA
High –0.3
0.7
1.7
2.7
0.7
1.7
12
12
1.8 V LVCMOS
8 mA
8 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45
VCCI – 0.45
8
8
1.5 V LVCMOS
4 mA
4 mA
High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI
4
4
3.3 V PCI
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Notes:
1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the
equivalent software default drive strength. These values are for normal ranges only.
2. Currents are measured at 125°C junction temperature.
3. Output slew rate can be extracted using the IBIS Models.
4. Output drive strength is below JEDEC specification.
5. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.



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