VMV3 datasheet(43/212 Pages) MICROSEMI

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Military ProASIC3/EL Low Power Flash FPGAs

Revision 3

2-29

1.5 V Core Voltage

Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings

–1 Speed Grade, Military-Case Conditions: TJ = 125°C, VCC = 1.425 V, Worst Case VCCI

Applicable to Pro I/Os for A3PE600L and A3PE3000L Only

Standard

3.3 V LVTTL /

3.3 V LVCMOS

12 mA

12 mA High

– 0.52 1.97 0.03 1.23 1.78 0.34 1.99 1.46 2.63 2.89 3.23 2.71

3.3 V LVCOMS

Wide Range3

100 µA

12 mA High

– 0.52 2.89 0.03 1.61 2.44 0.34 2.88 2.12 3.89 4.25 4.12 3.36

2.5 V LVCMOS

12 mA

12 mA High

– 0.52 2.01 0.03 1.49 1.93 0.34 2.02 1.65 2.71 2.78 3.27 2.89

1.8 V LVCMOS

12 mA

12 mA High

– 0.52 2.24 0.03 1.44 2.14 0.34 2.26 1.84 3.02 3.41 3.51 3.08

1.5 V LVCMOS

12 mA

12 mA High

– 0.52 2.60 0.03 1.60 2.35 0.34 2.62 2.14 3.21 3.52 3.87 3.39

3.3 V PCI

Per PCI

spec

–High 10 254 0.52 2.25 0.03 2.03 2.88 0.34 2.27 1.58 2.64 2.89 3.52 2.83

3.3 V PCI-X

Per PCI-X

spec

–High 10 254 0.52 2.25 0.03 2.03 2.88 0.34 2.27 1.58 2.64 2.89 3.52 2.83

3.3 V GTL

20 mA5 20 mA5 High 10 25 0.52 1.68 0.03 1.79 – 0.34 1.58 1.68

–

2.83 2.92

2.5 V GTL

20 mA5 20 mA5 High 10 25 0.52 1.72 0.03 1.73 – 0.34 1.69 1.72

–

2.93 2.97

3.3 V GTL+

35 mA

35 mA High 10 25 0.52 1.66 0.03 1.79 – 0.34 1.63 1.66

–

2.88 2.90

2.5 V GTL+

33 mA

33 mA High 10 25 0.52 1.75 0.03 1.73 – 0.34 1.76 1.69

–

3.00 2.94

HSTL (I)

8 mA

High 20 25 0.52 2.57 0.03 2.14 – 0.34 2.59 2.55

–

3.84 3.79

HSTL (II)

15 mA5 15 mA5 High 20 50 0.52 2.44 0.03 2.14 – 0.34 2.46 2.19

–

3.71 3.43

SSTL2 (I)

15 mA

15 mA High 30 25 0.52 1.68 0.03 1.58 –

034 1.69 1.46

–

1.69 1.46

SSTL2 (II)

18 mA

18 mA High 30 50 0.52 1.72 0.03 1.58 – 0.34 1.73 1.39

–

1.73 1.39

SSTL3 (I)

14 mA

14 mA High 30 25 0.52 1.83 0.03 1.51 – 0.34 1.84 1.45

–

1.84 1.45

SSTL3 (II)

21 mA

21 mA High 30 50 0.52 1.63 0.03 1.51 – 0.34 1.64 1.31

–

1.64 1.31

LVDS

24 mA

–

High

–

– 0.52 1.48 0.03 1.86 –

–

LVPECL

24 mA

–

High

–

– 0.52 1.40 0.03 1.61 –

–

Notes:

1. Note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will not operate at the

equivalent software default drive strength. These values are for normal ranges only.

2. Output delays provided in this table were extracted with an output load indicated in the Capacitive Load column. For a

specific output load, refer to Designer software.

3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.

4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-15 on page 2-73 for

connectivity. This resistor is not required during normal operation.

5. Output drive strength is below JEDEC specification.

6. For specific junction temperature and voltage supply levels, refer to Table 2-5 on page 2-8 for derating values.

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