AD-DPGIOZ datasheet(45/61 Pages) AD

45 / 61 page

Data Sheet

AD9961/AD9963

Rev. A | Page 45 of 60

DEVICE CLOCKING

CLOCK DISTRIBUTION

The clock distribution diagram shown in Figure 65 gives an

overview of the clocking options for each of the data converters.

The receive path ADCs and the transmit path DACs can be

clocked directly from the CLKP/CLKN inputs or from the

output of the on-chip DLL. The auxiliary ADC sampling clock

is always a divided down version of the input clock. The

auxiliary DACs are updated synchronously with the serial port

clock and have no relationship with the CLKP/CLKN inputs.

The best data converter performance is realized when a low

jitter clock source drives the CLKP/CLKN inputs, and this

signal is used directly (or through the on-chip divider) as the

data converter sampling clocks. The ADC and DAC sampling

clocks are independently selected to be derived from either the

CLKP/CLKN input or from the DLL output, DLLCLK. Using

DLLCLK as the data converter sampling clock signal may

degrade the noise and SFDR performance of the converters.

More information is given in the Clock Multiplication Using the

DLL section.

The receive path ADC has a duty cycle stabilizer (DCS) to help

make the ADC performance insensitive to changes in the input

clock duty cycle. The DCS can be bypassed. Recommendations

for using the DCS can be found in the Clock Duty Cycle

Considerations section.

The ADC clock divider and the DLL clock multiplication

supports a variety of ratios between the receive path ADC

sampling clock and the transmit path DAC sampling clock.

Table 21 details the specific values the device supports and

which register bits are require configuration.

Table 21. Clock Tree Configuration Variables

Variable

Values

Address

Bit(s)

DCS_BP

0 or1

0x66

ADCDIV

1, 2, 4

0x66

[1:0]

ADCCLKSEL

0 or 1

0x71

DACCLKSEL

0 or 1

0x71

1 to 6, 8

0x71

[3:0]

1, 2, 3,…, 32

0x72

[4:0]

DLLDIV

1, 2, 4

0x72

[6:5]

AUXDIV

2J, J = 1 to 8

0x7A

[2:0]

CLKP

CLKN

DLL

ADCCLK

DACCLK

ADCCLKSEL

÷DLLDIV

AUXCLK

DACCLKSEL

EXTDLLCLK

DCS_BP

CLK_PD

ADC

DAC

AUXADC

DLLCLK

DCS

÷AUXDIV

DOUBLER

AND

÷ADCDIV

Figure 65. Clock Distribution Diagram

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