AD-DPGIOZ datasheet(47/61 Pages) AD

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Data Sheet

AD9961/AD9963

Rev. A | Page 47 of 60

÷M

CHARGE

PUMP

DLL_RESB

REG 0x75[3]

SELECT

LOGIC

PHASE

DETECTOR

÷DLLDIV

÷N

REFCLK

DLLCLK

EXTDLLCLK

MCLK

DLLFILT

PIN 54

DELAY LINE

DLL_EN

REG 0x60[7]

DLL_REF_EN

REG 0x71[4]

DLLLOCKED

REG 0x72[7]

DLLBIASPD

REG 0x61[5]

M[4:0]

REG 0x72[4:0]

DLLDIV[1:0]

REG 0x72[6:5]

M[3:0]

REG 0x71[3:0]

Figure 70. Functional Block Diagram of Clock Multiplier DLL

The DLL is composed of a ring oscillator made from a

programmable delay line. The ring oscillator output signal is

labeled as MCLK. The MCLK signal is set to oscillate at a

frequency M times greater than the REFCLK signal. The DLL

output clock, DLLCLK, is the MCLK signal divided by a

programmable factor, N. M can be set to values from 1 to 32

and N can be set to values from 1 to 6 and 8.

DLL Frequency Locking Range

The DLL frequency lock range is determined by the output

frequency of the ring oscillator, MCLK. The DLL locks over an

MCLK frequency range of 100 MHz to 310 MHz. Verifying that

the DLL is locked can be done by polling the DLL_Locked bit

(Register 0x72, Bit 7).

DLL Filter Considerations

The DLL requires an external loop filter between the DLLFILT

pin (Pin 54) and ground for stable operation. The circuit

diagram in Figure 71 shows the recommended DLL filter

configuration. The external components should be placed as

close as possible to the device pins. It is important that no noise

be coupled into the filter circuit or DLL output clock jitter

performance is degraded.

22.5Ω

820pF

68nF

DLLFILT

Figure 71. Recommended DLL Loop Filter

DLL Start-Up Routine

To enable the DLL, three bits should be set. The DLL_EN bit

(Register 0x60, Bit 7) and the DLL_REF_EN bit (Register 0x71,

Bit 4) should be set to 1 and the DLLBIAS_PD bit (Register

0x61, Bit 5) should be set to 0.

The CLK input signal should be stable. The DLL_RESB bit

should be asserted low for a minimum of 25 µs, and then

brought inactive (high) to start the frequency acquisition. The

DLL takes several REFCLK cycles to acquire lock. The

DLL_Locked bit can be queried to verify the DLL is locked.

CONFIGURING THE CLOCK DOUBLERS

The receive and transmit data paths each have a clock doubler

used for clocking data through the device. These clock doublers

are only used in single data rate clocking mode, when there is

no interpolation or decimation being used.

These doublers should be configured according to the following

guidelines.

operating points of the doublers and should be initialized with

the following values:

0x3A = 0x55, 0x3B = 0x55, 0x3C = 0x00

The clock doubler mode and pulse widths should be configured

based on the DAC and ADC sample rates. These should be

configured according to Table 22.

Table 22. Clock Doubler Configuration Guidelines

DACCLK/ADCCLK Freq (MHz)

TXDBLSEL

Bit 0

TX_DBLPW[2:0]

Bits[5:3]

RXDBLSEL

Bit 1

RX_DBLPW[2:0]

Bits[2:0]

DCS_BP1

Bit 2

0 to 15

111

15 to 30

111

30 to 45

110

45 to 55

101

55 to 65

100

65 to 70

011

70 to ≥70

1 The DCS_BP bit should be set based on the AUXADCCLK frequency.

2 X = don’t care.

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