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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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APA600 데이터시트(PDF) 70 Page - Actel Corporation |
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APA600 데이터시트(HTML) 70 Page - Actel Corporation |
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70 / 178 page  ProASICPLUS Flash Family FPGAs 2- 60 v5.9 Synchronous SRAM Write Note: The plot shows the normal operation status. Figure 2-33 • Synchronous SRAM Write Table 2-57 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS ↑ 0.5 ns DCS DI setup to WCLKS ↑ 1.0 ns WACH WADDR hold from WCLKS ↑ 0.5 ns WDCS WADDR setup to WCLKS ↑ 1.0 ns WPCA New WPE access from WCLKS ↑ 3.0 ns WPE is invalid while PARGEN is active WPCH Old WPE valid from WCLKS ↑ 0.5 ns WRCH, WBCH WRB & WBLKB hold from WCLKS ↑ 0.5 ns WRCS, WBCS WRB & WBLKB setup to WCLKS ↑ 1.0 ns Note: On simultaneous read and write accesses to the same location, DI is output to DO. WCLKS WPE WADDR, DI WRB, WBLKB Cycle Start tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCML tCCYC |
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