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APA600 데이터시트(PDF) 25 Page - Actel Corporation |
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APA600 데이터시트(HTML) 25 Page - Actel Corporation |
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25 / 178 page ![]() ProASICPLUS Flash Family FPGAs v5.9 2-15 Figure 2-15 • Using the PLL to Delay the Input Clock Figure 2-16 • Using the PLL to Advance the Input Clock ÷n ÷m ÷u ÷v D D D D PLL Core External Feedback Global MUX B OUT Global MUX A OUT GLB GLA 0˚ 180˚ 133 MHz 133 MHz ÷1 ÷1 ÷1 ÷n ÷m ÷u ÷v D D D D PLL Core External Feedback Global MUX B OUT Global MUX A OUT GLB GLA 0˚ 180˚ 133 MHz 133 MHz ÷1 ÷1 ÷1 |
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