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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM8L152M8 데이터시트(PDF) 63 Page - STMicroelectronics |
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STM8L152M8 데이터시트(HTML) 63 Page - STMicroelectronics |
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63 / 134 page  DocID17943 Rev 6 63/134 STM8L15xx8, STM8L15xR6 Option bytes 64 Table 13. Option byte description Option byte no. Option description OPT0 ROP[7:0] Memory readout protection (ROP) 0xAA: Disable readout protection (write access via SWIM protocol) Refer to Readout protection section in the STM8L reference manual (RM0031). OPT1 UBC[7:0] Size of the user boot code area UBC[7:0] Size of the user boot code area 0x00: No UBC 0x01: Page 0 reserved for the UBC and write protected. ... 0xFF: Page 0 to 254 reserved for the UBC and write-protected. Refer to User boot code section in the STM8L reference manual (RM0031). OPT2 PCODESIZE[7:0] Size of the proprietary code area 0x00: No proprietary code area 0x01: Page 0 reserved for the proprietary code and read/write protected. ... 0xFF: Page 0 to 254 reserved for the proprietary code and read/write protected. Refer to Proprietary code area (PCODE) section in the STM8L reference manual (RM0031) for more details. OPT3 IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware IWDG_HALT: Independent watchdog off in Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode WWDG_HW: Window watchdog 0: Window watchdog activated by software 1: Window watchdog activated by hardware WWDG_HALT: Window window watchdog reset on Halt/Active-halt 0: Window watchdog stopped in Halt mode 1: Window watchdog generates a reset when MCU enters Halt mode OPT4 HSECNT: Number of HSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles LSECNT: Number of LSE oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles |
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