STM8L152M8 datasheet(102/134 Pages) STMICROELECTRONICS

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Electrical parameters

STM8L15xx8, STM8L15xR6

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DocID17943 Rev 6

9.3.8

Communication interfaces

SPI1 - Serial peripheral interface

Unless otherwise specified, the parameters given in Table 43 are derived from tests

performed under ambient temperature, fSYSCLK frequency and VDD supply voltage

conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on

the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

Table 43. SPI1 characteristics

Symbol

Parameter

Conditions(1)

Min.

Max.

Unit

fSCK

1/tc(SCK)

SPI1 clock frequency

Master mode

MHz

Slave mode

tr(SCK)

tf(SCK)

SPI1 clock rise and fall

time

Capacitive load: C = 30 pF

tsu(NSS)(2)

NSS setup time

Slave mode

4 x 1/fSYSCLK

th(NSS)(2)

NSS hold time

Slave mode

tw(SCKH)(2)

tw(SCKL)(2)

SCK high and low time

Master mode,

fMASTER = 8 MHz, fSCK= 4 MHz

105

145

tsu(MI) (2)

tsu(SI)(2)

Data input setup time

Master mode

Slave mode

th(MI) (2)

th(SI)(2)

Data input hold time

Master mode

Slave mode

ta(SO)(2)(3)

Data output access time

Slave mode

3x 1/fSYSCLK

tdis(SO)(2)(4) Data output disable time

Slave mode

tv(SO) (2)

Data output valid time

Slave mode (after enable edge)

tv(MO)(2)

Data output valid time

Master mode (after enable

edge)

-20

th(SO)(2)

Data output hold time

Slave mode (after enable edge)

th(MO)(2)

Master mode (after enable

edge)

1. Parameters are given by selecting 10 MHz I/O output frequency.

2. Values based on design simulation and/or characterization results, and not tested in production.

3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data.

4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z.

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