DAC5687IPZP datasheet(44/79 Pages) TI

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IOUTB1

IOUTB2

IOUTA1

IOUTA2

16-Bit

DAC

2fDATA

2 – 16 y fDATA

fDATA

16-Bit

DAC

2fDATA

FIR1

Edge Triggered

Input Latches

• ••

DA[15:0]

DEMUX

B0025-02

DA[15:0]

ts(DATA)

th(DATA)

TXENABLE

ts(TXENABLE)

CLK1 or

PLLLOCK

T0041-01

DA[15:0]

ts(DATA)

th(DATA)

QFLAG

CLK1 or

PLLLOCK

T0001-01

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

Figure 49. Interleave Bus Mode Data Path

Figure 50. Interleave Bus Mode Timing Diagram Using TXENABLE

Interleaved user data on data bus DA is alternately multiplexed to internal data channels A and B. Data channels

A and B can be synchronized using either the QFLAG pin or the TXENABLE pin. When qflag in register

config_usb is 0, transitions on TXENABLE identify the interleaved data sequence. The first data after the rising

edge of TXENABLE is latched with the rising edge of CLK as channel-A data. Data is then alternately distributed

to B and A channels with successive rising edges of CLK. When qflag is 1, the QFLAG pin is used as an output

to identify the interleaved data sequence. QFLAG high identifies data as channel B (see Figure 51).

Figure 51. Interleave Bus Mode Timing Diagram Using QFLAG

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