L6717 datasheet(53/56 Pages) STMICROELECTRONICS

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L6717

Layout guidelines

Doc ID 17326 Rev 1

53/56

For heat dissipation, place copper area under the IC. This copper area must be connected

with internal copper layers through several VIAs to improve the thermal conductivity. The

combination of copper pad, copper plane and VIAs under the controller allows the device to

reach its best thermal performances.

13.2

Small signal components and connections

These are small signal components and connections to critical nodes of the application as

well as bypass capacitors for the device supply. Locate the bypass capacitor close to the

device and refer sensible components such as frequency set-up resistor ROSC, offset

resistor and OVP resistor ROVP to SGND (when applicable). Star grounding is suggested:

use the device exposed PAD as a connection point.

VSEN pin filtered vs. SGND helps in reducing noise injection into device and EN pin filtered

vs. SGND helps in reducing false trip due to coupled noise: take care in routing driving net

for this pin in order to minimize coupled noise.

Remote buffer connection must be routed as parallel nets from the FBG/FBR pins to the

load in order to avoid the pick-up of any common mode noise. Connecting these pins in

points far from the load will cause a non-optimum load regulation, increasing output

tolerance.

Locate current reading components close to the device. The PCB traces connecting the

reading point must use dedicated nets, routed as parallel traces in order to avoid the pick-up

of any common mode noise. It's also important to avoid any offset in the measurement and,

to get a better precision, to connect the traces as close as possible to the sensing elements.

Symmetrical layout is also suggested. Small filtering capacitor can be added, near the

controller, between VOUT and SGND, on the CSxN line when reading across inductor to

allow higher layout flexibility.

L6717 데이터시트(PDF) 53 Page - STMicroelectronics