L6717 datasheet(28/56 Pages) STMICROELECTRONICS

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Power manager I2C

L6717

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Doc ID 17326 Rev 1

Table 12.

Power manager I2C command phase and data stream

Command

code [4:6]

Data stream

[1:8]

Description

1CN

[1:2] xx

[3] SIGN

[4:8] OVRSPD

OVERSPEEDING: Adds a positive/negative offset to the regulation

according to the SIGN bit with 50mV LSB and 5bit resolution.

[3] SIGN: 1b for positive offset, 0b for negative offset.

Negative offset is applicable only to CORE section (NB does not react

to negative OS command)

[4:8] OVRSPD: 5bit code (4:MSB to 8:LSB), defines the offset to add

to the programmed reference (VID).

Maximum CORE output voltage reachable is limited to 2.8V.

Maximum NB output voltage reachable is limited by the Maximum NB

Offset: +600mV (over VID)

“CN” bits in command code address CORE section (“C” bit) or NB

section (“N” bit) if set to 1b. Asserting both C and N bits will apply the

command to both CORE and NB section.

See Table 13 for details about OVRSPD codification.

000

[1:4] xxxx

[5:6] OV_NB

[7:8] OV_CORE

OV_SET: Overvoltage threshold setup for CORE and/or NB sections.

Sets the OV threshold above the programmed VID (including

OVRSPD) in with three 200mV steps from + 250mV up to +850mV

(up to 650mV for NB).

[1:4]: ignored

[5:6] OV_NB: NorthBridge OVP. 2bit code, defines the OV threshold

for the NB section above the programmed reference (VID).

[7:8] OV_CORE: Core OVP. 2bit code, defines the OV threshold for

the CORE section above the programmed reference (VID).

Default OV threshold is +250mV above reference for both sections.

See Table 14 for details about OV_SET codification.

001

[1:5] xxxxx

[6:8] FSW

FSW_ADJ: Switching frequency adjustment. Modifies the switching

frequency programmed through OSC pin according to FSW code by

+/- 10% or +/-20%.

[1:5]: ignored

[6:8]: FSW: Switching frequency adjustment. 3 bits code to adjust the

switching frequency with respect programmed voltage.

See Table 15 for details about FSW_ADJ codification.

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