SCF5250LPV100 datasheet(23/56 Pages) FREESCALE

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SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

Table 17 provides the linear regulator operating specifications for the SCF5250 processor.

Table 18 provides the DC electrical specifications.

Table 17. Linear Regulator1 Operating Specification

1 A pmos regulator is employed as a current source in this Linear regulator, so a 10µF capacitor (ESR 0 ... 5 Ohm) is needed on the output pin

(LINOUT) to integrate the current. Typically this will require the use of a Tantalum type capacitor.

Characteristic

Symbol

Min

Typ

Max

Input Voltage

Vin

3.0V

3.3V

3.6

Output Voltage (LINOUT)

Vout

1.14V

1.2V

1.26V

Output Current

Iout

–

100mA

150mA

Power Dissipation

–

436uW

Load Regulation (10% Iout

≥ 90% Iout)

–

40mV

50mV

60mV

Power Supply Rejection

PSRR

–

40dB

–

Table 18. DC Electrical Specifications (I/O Vcc = 3.3 Vdc + 0.3 Vdc)

Characteristic

Symbol

Min

Max

Units

Operation Voltage Range for I/O

Vcc

3.0

3.6

Input High Voltage

VIH

25.5

Input Low Voltage

VIL

-0.3

0.8

Input Leakage Current @ 0.0 V /3.3 V During Normal Operation

Iin

–

±1µµA

Hi-Impedance (Three-State) Leakage Current

@ 0.0 V/3.3 V During Normal Operation

ITSI

–

±1µµA

Output High Voltage IOH = 8mA

1, 4mA2, 2mA3

VOH

2.4

–

Output Low Voltage IOL = 8mA

1, 4mA2, 2mA3

VOL

–0.4

Schmitt Trigger Low to High Threshold Point6

VT+

1.47

–

Schmitt Trigger High to Low Threshold Point6

VT-

–.95

Load Capacitance (DATA[31:16], SCLK[4:1], SCLKOUT, EBUOUT[2:1],

LRCK[3:1], SDATAO[2:1], CFLG, EF, DDATA[3:0], PST[3:0], PSTCLK,

IDE-DIOR, IDE-DIOW, IORDY)

–50

Load Capacitance (ADDR[24:9], BCLK)

–40

Load Capacitance (BCLKE, SDCAS, SDRAS, SDLDQM, SD_CS0, SDUDQM,

SDWE, BUFENB[2:1])

–30

Load Capacitance (SDA0, SDA1, SCL0, SCL1, CMD_SDIO2, SDATA2_BS2,

SDATA1_BS1, SDATA0_SDIO1, CS0/CS4, CS1, OE, R/W, TA, TXD[1:0], XTRIM,

TDO/DSO, RCK, SFSY, SUBR, SDATA3, TOUT0, QSPID_OUT, QSPICS[3:0],

GP[6:5])

–20

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