SCF5250LPV100 datasheet(32/56 Pages) FREESCALE

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SCF5250 Data Sheet: Technical Data, Rev. 1.3

Freescale Semiconductor

Figure 9 provides the I2C-bus and system clock timing diagram and Table 28 provides the I2C-bus output

timing parameters.

Figure 9. I2C and System Clock Timing Relationship

Table 28. I2C Output Bus Timings

Num

Characteristic

96 MHz

Units

Min

Max

M101

1 SCL and SDA are internally synchronized. This setup time must be met only if recognition on a particular clock is required.

SCL, SDA Valid to BCLK (input setup)

–

M11

BCLK to SCL, SDA Invalid (input hold)

4.5

–

M122

2 Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL

or SDA are driven low by the processor. The time required for SCL or SDA to reach a high level depends on external signal capacitance and

pull-up resistor values.

BCLK to SCL, SDA Low (output valid)

–

M133

3 Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL

or SDA are actively being driven or held low by the processor.

BCLK to SCL, SDA Invalid (output hold)

–

BCLK

SCL, SDA IN

SCL, SDA OUT

M10

M11

M12

M13

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