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ZIOL2102 데이터시트(PDF) 61 Page - List of Unclassifed Manufacturers

부품명 ZIOL2102
상세설명  IO-Link compliant HV Line Driver IC Family
PDF  91 Pages
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ZIOL2xxx – IC Family
IO-Link compliant HV Line Driver IC Family
Data Sheet
January 31, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 2.2.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
61 of 90
min
,
,
max
,
_
,
min
2
1
OUT
Sw
set
OUT
HV
DD
set
OUT
I
f
V
V
V
L
,
where IOUT,min is the lowest output current, VDD_HV,max is the highest input voltage and fSw is the switching frequency
of the DC/DC converter.
3.6.4.
PCB Layout considerations
To achieve optimal parameters for the DC/DC converter (e.g. efficiency or ripple voltage), attention has to be
given to the PCB layout. Figure 3.23 shows the DC/DC converter, its external elements and two high frequency
loops. The length of each loop has to be as short as possible. Furthermore, the distance between SW and FB has
to be as large as possible to decrease the interference. It is recommended to have ground planes in between
each signal line.
Figure 3.23 High frequency critical loops of DC/DC converter for PCB layout
L1
D1
C1
R1
R2
C5
SW
FB
VDD
C2
Loop 1
Loop 2
VDD_HV
VOUT



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