ZIOL2102 datasheet(65/91 Pages) ETC2

65 / 91 page

ZIOL2xxx – IC Family

IO-Link compliant HV Line Driver IC Family

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

65 of 90

Figure 4.3 Power Line Fail Detection

ZIOL2401

AUX_EN

AUX_TX

WURQ

TX_EN

INT_L

RST_L

PFD

VDD

COM_O

VSS

LR_IN

LR_OUT

COM_I

AUX_O

Standard

Cable

Device (Sensor)

Vout

DC_RDY

L+

L-

C/Q

AUX_I

AUX_RX

R3 and R4 which perform

the line voltage sensor

shall connected directly to

the cable (L+/L-).

The PCB layout design requires considering several recommendations. In particular the placement of decoupling

capacitors and the placement external components that perform the DC/DC converter circuits shall be done

carefully. Recommendations are:



Low resistive and low inductive ground interconnections due to metal ground areas surrounding the IC

or/and using a special “Ground” PCB layer.



The wiring of the channel driver output shall consider that the wires are designed for currents up to

500mA (depending on the IC configuration) and in combination with that wiring for VDD and VSS shall

designed for currents up to 1A.



Decoupling capacitors related to the IC pins VDD and LR_OUT (and LR_IN if applicable) shall placed

as close as possible to the IC pin.



The DC/DC converter requires an external Schottky-diode as free-wheel diode. Its anode shall be

interconnected to the SW pin. It is important that its cathode has good (short) ground connection. With

respect to all to the SW pin interconnected devices (free-wheel diode and inductor L1) all wires have to

be kept as short as possible. Moreover, the PCB design shall make sure that the parasitic coupling

between the node belonging to the SW pin and the node belonging to the FB pin of the IC is

minimized.

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