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ADF7021 데이터시트(PDF) 59 Page - Analog Devices |
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ADF7021 데이터시트(HTML) 59 Page - Analog Devices |
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59 / 64 page ![]() Data Sheet ADF7021 Rev. B | Page 59 of 64 REGISTER 13—3FSK/4FSK DEMOD REGISTER Refer to the Receiver Setup section for information about programming these settings. 3FSK_CDR_THRESHOLD 3FSK/4FSK_ SLICER_THRESHOLD CONTROL BITS 3FSK_PREAMBLE_ TIME_VALIDATE 4 BITS 0 0 1 1 VM2 VITERBI PATH MEMORY VM1 0 1 0 1 6 BITS 8 BITS 32 BITS PHASE CORRECTION 0 DISABLED 1 ENABLED PC1 3FSK VITERBI DETECTOR 0 DISABLED 1 ENABLED VD1 ST3 0 0 0 . . 1 ST1 1 0 1 . . 1 SLICER THRESHOLD 1 2 3 . . ST2 0 1 1 . . 1 ST7 0 0 0 . . 1 ... ... ... ... ... ... ... 127 0 0 0 ... 0 OFF VT3 0 0 0 . . 1 VT1 1 0 1 . . 1 3FSK CDR THRESHOLD 1 2 3 . . VT2 0 1 1 . . 1 VT7 0 0 0 . . 1 ... ... ... ... ... ... ... 127 0 0 0 ... 0 OFF PTV3 0 0 0 . . 1 PTV1 1 0 1 . . 1 3FSK PREMABLE TIME VALIDATE 1 2 3 . . PTV2 0 1 1 . . 1 PTV4 0 0 0 . . 1 15 0 0 0 0 0 Figure 75. Register 13—3FSK/4FSK Demod Register Map |
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