ICS1531 datasheet(67/76 Pages) ICST

부품명	ICS1531

상세설명	Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator

PDF	76 Pages

Scroll/Zoom	100%

제조업체	ICST [Integrated Circuit Systems]

홈페이지	http://www.icst.com

Logo

67 / 76 page

Chapter 10

Timing Diagrams

ICS1531 Rev N 12/1/99

December, 1999

ICS1531 Data Sheet - Preliminary

10.3

AC Timing Diagrams

10.3.1

Phase-Locked-Loop Timing for Digital Setup and Hold

The input HSYNC signal is used to generate the REF output signal. In the Phase/Frequency Detector, the

REF signal is compared with ADCSYNC (which provides the recovered HSYNC signal). Table 10-3 gives

the timing for these signals, and Figure 10-5 shows timing characteristics.

Figure 10-5.

Timing for Phase-Locked Loop

Table 10-3.

Phase-Locked-Loop Timing

Time

Period

Timing Description

Min

Typ

Max

Units

Input HSYNC Rise Time to

REF Rise Time

TBD

Clock Period

Clock Duty Cycle

45-55

50-50

55-45

ADCSYNC Active Time

× Tp

Input HSYNC Frequency

Result from:

Section 6.5.3, “Register 02h:

Fdbk Div 0 Register” and

Section 6.5.4, “Register 03h:

Fdbk Div 1 Register”

HSYNC

CLK

ADCSYNC

REF

ICS1531 데이터시트(PDF) 67 Page - Integrated Circuit Systems

ICS1531 데이터시트(HTML) 67 Page - Integrated Circuit Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76

데이터시트 다운로드

링크 URL