80960HA datasheet(72/102 Pages) INTEL

부품명	80960HA

상세설명	80960HA/HD/HT 32-Bit High-Performance Superscalar Processor

PDF	102 Pages

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72 / 102 page

80960HA/HD/HT

Advance Information Datasheet

The processor can stall (BSTALL asserted) even with an empty bus queue (BREQ deasserted).

Depending on the instruction stream and memory wait states, the two signals can be separated by

several CLKIN cycles.

Bus arbitration logic that logically “ANDs” BSTALL and BREQ will not correctly grant the bus to

the processor in all stall cases, potentially degrading processor performance.

Do not logically “AND” BSTALL and BREQ together in arbitration logic. Instead, the simplest

bus arbitration should logically “OR” BSTALL and BREQ to determine the processor’s bus

ownership requirements.

More sophisticated arbitration should recognize the priority nature of these two signals. Using a

traffic light analogy, BREQ is a “yellow light” warning of a possible processor stall and BSTALL

is a “red light” indicating a stall in progress.

Figure 49. BREQ and BSTALL Operation

CLKIN

ADS

BLAST

BREQ

BSTALL

80960HA 데이터시트(PDF) 72 Page - Intel Corporation