ADV7341_15 datasheet(86/108 Pages) AD

86 / 108 page

ADV7340/ADV7341

Data Sheet

Rev. C | Page 86 of 108

Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)

In this mode, the ADV7340/ADV7341 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the

field input indicates a new frame, that is, vertical retrace. The ADV7340/ADV7341 automatically blank all normally blank lines as

required by the CCIR-624 standard. Pixel data is latched on the rising clock edge following the timing signal transitions. HSYNC and

FIELD are output on the S_HSYNC and S_VSYNC pins, respectively.

Figure 105. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)

Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)

In this mode, the ADV7340/ADV7341 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC

inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The

ADV7340/ADV7341 automatically blank all normally blank lines as required by the CCIR-624 standard. HSYNC and VSYNC are input

on the S_HSYNC and S_VSYNC pins, respectively.

Figure 106. SD Slave Mode 2, NTSC

FIELD

PIXEL

DATA

HSYNC

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

HSYNC

VSYNC

HSYNC

VSYNC

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