전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

ADV7341 데이터시트(PDF) 97 Page - Analog Devices

부품명 ADV7341
상세설명  Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS
PDF  108 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

ADV7341 데이터시트(HTML) 97 Page - Analog Devices

Back Button ADV7341_15 Datasheet HTML 93Page - Analog Devices ADV7341_15 Datasheet HTML 94Page - Analog Devices ADV7341_15 Datasheet HTML 95Page - Analog Devices ADV7341_15 Datasheet HTML 96Page - Analog Devices ADV7341_15 Datasheet HTML 97Page - Analog Devices ADV7341_15 Datasheet HTML 98Page - Analog Devices ADV7341_15 Datasheet HTML 99Page - Analog Devices ADV7341_15 Datasheet HTML 100Page - Analog Devices ADV7341_15 Datasheet HTML 101Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 97 / 108 page
background image
Data Sheet
ADV7340/ADV7341
Rev. C | Page 97 of 108
Table 67. 10-Bit 525i YCrCb In (EAV/SAV), RGB and
CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x10
10-bit input enabled.
Table 68. 10-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x10
10-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 69. 20-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x18
20-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 70. 20-Bit 525i YCrCb In, RGB and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x88
0x18
20-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 71. 30-Bit 525i RGB In, YPrPb and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. YPrPb and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x87
0x80
RGB input enabled.
0x88
0x10
10-bit input enabled (10 × 3 = 30-bit).
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 72. 30-Bit 525i RGB In, RGB and CVBS/Y-C Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0xFC
All DACs enabled. PLL enabled (16×).
0x01
0x00
SD input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x80
0x10
NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9
Pixel data valid. RGB and CVBS/Y-C
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
0x87
0x80
RGB input enabled.
0x88
0x10
10-bit input enabled (10 × 3 = 30-bit).
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com