AN4035 datasheet(12/42 Pages) STMICROELECTRONICS

12 / 42 page

JTAG

AN4035

12/41

Doc ID 022669 Rev 2

Note:

If the shadow flash block is erased without reprogramming a new valid password before a

reset, it contains an illegal password and the debug port is inaccessible.

Subsequent resets clear the JTAG censor password register and the Nexus client TAP

controller holds in reset again. Therefore, the tool must resend the JTAG serial

password, as described above, in order to enable the Nexus client TAP controller

again.

2.5.1

CENSOR_CTRL register

The CENSOR_CTRL register is an shift register path from TDI to TDO selected when the

ENABLE_CENSOR_CTRL instruction is active. The CENSOR_CTRL register transfers its

value to a parallel hold register on the rising edge of TCK when the TAP controller state

machine is in the Update-DR state. The parallel hold register bits CENSOR_CTRL

correspond directly to the JTAGC output control internal signals jtag_censor_ctrl. The

jtag_censor_ctrl signals are used to control chip dependent censorship features. Once the

ENABLE_CENSOR_CTRL instruction is executed, jtag_censor_ctrl remains valid until a

JTAGC reset occurs.

AN4035 데이터시트(PDF) 12 Page - STMicroelectronics