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AN4035 데이터시트(PDF) 19 Page - STMicroelectronics

부품명 AN4035
상세설명  Flash programming through
PDF  42 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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AN4035 데이터시트(HTML) 19 Page - STMicroelectronics

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AN4035
On-Chip Emulation (OnCE)
Doc ID 022669 Rev 2
19/41
Figure 11.
Signal transitions for writing OCMD to select a read from DBCR0
Figure 12 shows reading the value 0x80000000 from DBCR0 through the DR path
assuming the TAP controller state machine is initially in the RUN-TEST/IDLE state. The
state machine is returned to the RUN-TEST/IDLE state when the read is complete.
Figure 12.
Signal transitions for reading DBCR0
3.4
OnCE status register
The OnCE status register (OSR) is a special register in terms of how it is read. Status
information related to the state of the CPU is latched into the OnCE status register when the
OnCE TAP controller state machine enters the CAPTURE-IR state. The status information is
shifted out serially through the SHIFT-IR state on TDO. The OSR is a 10-bit register like the
OCMD. Therefore, the status information can be read while writing OCMD. The OSR is
shown in Figure 13.



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