AN4035 datasheet(27/42 Pages) STMICROELECTRONICS

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AN4035

On-Chip Emulation (OnCE)

Doc ID 022669 Rev 2

27/41

3.13.1

Software breakpoints

Recognition of software breakpoints by the OnCE module are enabled by setting the

OCR[FDB] bit along with the DBCR0[EDM] bit. Upon executing a bkpt pseudo-instruction,

the CPU enters debug mode after the instruction following the bkpt pseudo-instruction has

entered the instruction register. The bkpt pseudo-instruction is defined to be an all 0’s

instruction opcode.

3.13.2

Instruction address hardware breakpoints

The OnCE module provides the capability to set up to four instruction address hardware

breakpoints.

When an instruction address breakpoint is hit, the CPU enters debug mode prior to

executing the instruction at that address location. When debug mode is entered due to a

breakpoint, the CPUSCR holds the address at which the breakpoint was set in the PC, and

the IR contains the instruction at that address.

To use an instruction address hardware breakpoint, these steps are required:

Write the address at which a breakpoint is desired to one of the instruction address

compare registers IAC1, IAC2, IAC3, or IAC4.

Enable the instruction address compare debug event in the DBCR0 by setting the

appropriate enable bit; DBCR0[IAC1], DBCR0[IAC2], DBCR0[IAC3], or DBCR0[IAC4].

Exit from debug mode to normal execution to execute the desired code.

Poll the DBSR for the appropriate status bit to be set; DBSR[IAC1], DBSR[IAC2],

DBSR[IAC3], or DBSR[IAC4].

If the appropriate status bit in DBSR is set, verify entry into debug mode by reading the

OnCE status register.

Clear the appropriate status bit by writing a 1 to that bit location in the DBSR;

DBSR[IAC1], DBSR[IAC2], DBSR[IAC3], or DBSR[IAC4].

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