AN4035 datasheet(13/42 Pages) STMICROELECTRONICS

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AN4035

On-Chip Emulation (OnCE)

Doc ID 022669 Rev 2

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On-Chip Emulation (OnCE)

All of the SPC56x devices possess a OnCE module for debug control of the Power

Architecture® e200 core. The OnCE logic provides Nexus class 1 static debug capability

including run-time control, register access, and memory access to all memory-mapped

regions including on-chip peripherals, as well as providing access to the Nexus2 & Nexus3

configuration registers. The OnCE module is controlled by the JTAG signals through the

OnCE TAP controller.

Figure 4.

e200z OnCE block diagram

3.1

Enabling the OnCE TAP controller

Control of the OnCE module is obtained through the OnCE TAP controller. To enable the

OnCE TAP controller, the JTAGC must have control of the TAP and the

ACCESS_AUX_TAP_ONCE (0b10001) opcode must be loaded into the 5-bit JTAGC

instruction register with the JCOMP signal set to a logic 1.

The JTAGC instruction register is loaded by scanning in the appropriate bits on the TDI pin,

least significant bit (LSB) first, while in the SHIFT-IR state of the TAP controller state

machine. The last bit is shifted in with TMS set to a logical 1 causing transition from the

SHIFT-IR state to the EXIT1-IR state. Table 3-1 shows the steps required to enable the

OnCE TAP controller, assuming the TAP controller state machine is initially in the RUN-

TCK

e200z0_TMS

TDI

Test Access Port (TAP)

e200z0_TDO

Bypass Register

External Data Register

Controller

TAP Instruction Register

OnCE Mapped Debug Registers

Auxiliary Data Register

e200z0_TRST

(OnCE OCMD)

TDO Mux

Control

{

From

JTAGC

(to JTAGC)

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