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UPD17708 데이터시트(PDF) 221 Page - NEC

부품명 UPD17708
상세설명  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
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제조업체  NEC [NEC]
홈페이지  http://www.nec.com/
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UPD17708 데이터시트(HTML) 221 Page - NEC

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16.2.3 Clock control block
The clock control block controls generation of a clock when the internal clock is used (master operation) and clock
output timing.
The frequency fSC of the internal clock is set by the SIO0CK1 and SIO0CK0 flags of the serial I/O0 clock selection
register.
Figure 16-4 shows the configuration of the serial I/O0 clock selection register.
The shift clock output from the clock control block is valid only for the master operation (SIO0MS flag = 1).
For the clock generation timing, refer to the description of each communication mode.
Figure 16-4. Configuration of Serial I/O0 Clock Selection Register
Name
Flag symbol
b3
0
b2
S
B
M
D
b1
S
I
O
0
C
K
1
b0
S
I
O
0
C
K
0
Address
0BH
Read/Write
R/W
Serial I/O0 clock selection
Power-ON reset
WDT&SP reset
CE reset
Clock stop
00
0
0
0
0
0
0
0
0
0
0
0
93.75 kHz
375.00 kHz
281.25 kHz
46.875 kHz
Selects internal shift clock frequency fSC of serial interface 0
Continues processing
Slave reception mode is set automatically if acknowledge signal is not
received (fixed to “1” when serial I/O is selected)
Selects operation mode during slave transmission of I2C bus
Fixed to “0”
0
1
0
0
1
1
0
1
0
1



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