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UPD17708 데이터시트(PDF) 224 Page - NEC

부품명 UPD17708
상세설명  4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
PDF  356 Pages
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제조업체  NEC [NEC]
홈페이지  http://www.nec.com/
Logo NEC - NEC

UPD17708 데이터시트(HTML) 224 Page - NEC

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µPD17704, 17705, 17707, 17708, 17709
16.2.5 Presettable shift register 0
Presettable shift register 0 is an 8-bit shift register that writes serial out data and reads serial in data.
This register writes or reads data via data buffer.
It outputs the contents of the most significant bit (MSB) from the serial data I/O pin in synchronization with the falling
edge of the shift clock (during transmission operation), and reads data to the least significant bit (LSB) in synchronization
with the rising edge of the serial clock.
Figure 16-6 shows the configuration of the presettable shift register 0.
Figure 16-6. Configuration of Presettable Shift Register 0
Note
Data may be destroyed if the PUT or GET instruction is executed during serial communication. For details,
refer to 16.2.10 Causions on setting and reading data.
Name
b3
b2
b1
Symbol Peripheral register
b0
L
S
B
03H
Sets serial out data and reads serial in data
D7
← D6 ← D5 ← D4 ← D3 ← D2 ← D1 ← D0
Serial out
Serial in
Peripheral register
SIO0SFR
b7
M
S
B
b6
b5
b4
Presettable shift
register 0
Valid data
D7 D6 D5 D4 D3 D2 D1 D0
DBF3
Data buffer
Don't care
Transfer data
DBF2
Don't care
DBF1
DBF0
GETNote
8
PUTNote



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