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AN3142 데이터시트(PDF) 20 Page - STMicroelectronics |
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AN3142 데이터시트(HTML) 20 Page - STMicroelectronics |
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20 / 44 page ![]() Designing a fixed-off-time PFC AN3142 20/44 Doc ID 17005 Rev 3 4.3.7 L6563S biasing circuitry Following the dimensioning of the power components, the biasing circuitry for the L6563S is also described here. For reference, the internal schematic of the L6563S is represented below in Figure 11. For more detail on the internal functions please refer to the datasheet. Figure 11. L6563S internal schematic Pin 1 (INV): This pin is connected both to the inverting input of the E/A and to the OVP circuitry. A resistive divider is connected between the boost regulated output voltage and this pin. The internal reference on the non-inverting input of the E/A is 2.5 V (typ.), the output voltage (Vout) of the PFC pre-regulator is set at its nominal value, by the resistors ratio of the feedback output divider. RoutH and RoutL are then selected considering the desired nominal output voltage and the desired output power dissipated on the output divider. For example for a 50 mW output divider dissipation: Equation 39 With the commercial value selected RoutH = 3MΩ: Equation 40 mW 50 ) V 5 . 2 V ( R 2 OUT outH − = Ω = − = M 160 . 3 mW 50 ) V 5 . 2 V 400 ( R 2 outH 1 V 5 . 2 V R R out outL outH − = 159 1 V 5 . 2 V 400 R R outL outH = − = |
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