AN4506 datasheet(41/47 Pages) STMICROELECTRONICS

41 / 47 page

AN4506

First-in first-out (FIFO) buffer

DocID026442 Rev 2

41/47

way, the number of new data available in the FIFO does not depend on the previous

reading.

Follow these steps for Dynamic Stream mode configuration:

Turn on FIFO by setting the FIFO_En bit to “1” in the CTRL5 register (0x24). After this

operation the FIFO buffer is enabled but is not collecting data, output registers are

frozen to the last sample set loaded.

Activate Dynamic Stream mode by setting the FM[2:0] field to “110” in the FIFO_CTRL

6.3.5

Stream-to-FIFO mode

This mode is a combination of the Stream and FIFO modes described above. In Stream-to-

FIFO mode, the FIFO buffer starts operating in Stream mode and switches to FIFO mode

when the selected interrupt occurs.

Follow these steps for Stream-to-FIFO mode configuration:

Configure desired interrupt generator using register IG_CFG (0x30).

Turn on FIFO by setting the FIFO_En bit to “1” in the CTRL5 register (0x24). After this

operation the FIFO buffer is enabled but is not collecting data, output registers are

frozen to the last samples set loaded.

Activate Stream-to-FIFO mode by setting the FM[2:0] field to “011” in the FIFO control

The interrupt trigger is related to the IA bit in the IG_SRC register and it is generated even if

the interrupt signal is not driven to an interrupt pad. Switching modes is performed if both IA

and OVRN bits are set high. Stream-to-FIFO mode is sensitive to the trigger level and not to

the trigger edge; this means that if Stream-to-FIFO is in FIFO mode and the interrupt

condition disappears, the FIFO buffer returns to Stream mode because the IA bit becomes

zero. It is recommended to latch the interrupt signal used as the FIFO trigger in order to

avoid losing interrupt events. If the selected interrupt is latched, it is necessary to read the

In Stream mode the FIFO buffer continues filling, when the buffer is full, the OVRN bit is set

high and the next samples overwrite the oldest. When trigger occurs, two different cases

can be observed:

If the FIFO buffer is already full (OVRN = “1”), it stops collecting data at the first sample

after the trigger. FIFO content is composed of #30 samples collected before the trigger

event, the sample that has generated the interrupt event and one sample after trigger.

If FIFO is not full yet (initial transient), it continues filling until it is full (OVRN = “1”) and

then, if trigger is still present, it stops collecting data.

AN4506 데이터시트(PDF) 41 Page - STMicroelectronics