ST7FLITE0 configuration

AN1753

8/22

DocID9986 Rev 2

PWM0 CONTROL/STATUS REGISTER (PWM0CSR):

•

CMPF0: indicates that the upcounter value matches the DCR register value:

–

0: the upcounter value does not match the DCR value.

–

1: the upcounter value matches the DCR value.

PWM OUTPUT CONTROL REGISTER (PWMCR):

•

OE0: When set to 1, the PWM0 output is enabled

Timer initialization

Write to DCRx registers with the required value. The Output Compare function must be

enabled. To do this, reset the OE bit in the PWMCR register: this will disable the PWM

output.

To configure fcounter = fcpu, set CK1=1 and CK0=0 an

To enable the CMPF interrupt, set CMPIE=1 in the ATCSR register.

CMPF0

0

0

0

0

0

0

OP0

0

0

0

OE0

0

0

0

0