AN3181

Class B solution structure

Doc ID 17286 Rev 2

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Figure 9.

RAM startup self test structure

4.2.5

Clock startup self test

When the test begins, first the low speed internal clock (LSI) source is started, then the high

speed external source (HSE). The CPU is running on the high speed internal source (HSI).

HSI is switched onto a dedicated timer input, mainly TIM3, but TIM1 or TIM2 can also be

used on some devices. The timer is gated by the LSI source. The number of gated ticks is

compared and if it falls outside of the predefined interval (more than +/- 25% from nominal

value) an HSI fail is signaled and FailSafe() routine is called. CPU clock continues with HSI,

default source. If there is no error, the test continues with the next step and HSE is checked.

HSE is switched on as the new CPU clock source and input into the dedicated timer. The

same measurement and check of gated ticks are repeated but with HSE feeding the timer. If

the measure falls out of the interval, CPU clock is immediately turned back to HSI and HSE

fail is signaled with a FailSafe() routine being called. Otherwise, the test returns OK. CPU

clock is switched back to default HSI source after the test is finished. All the parts of this test

are under conditional compilation control, so the user can skip over some test e.g. HSE test

when no external oscillator is used.