AN3311 datasheet(16/58 Pages) STMICROELECTRONICS

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STM3210C-EVAL demonstration board

AN3311

16/58

Doc ID 18209 Rev 1

4.5

Clock source

Two clock sources are available on the STM3210C-EVAL demonstration board for

STM32F107VC, and RTC is embedded.

●

X2, 32 kHz crystal for embedded RTC

●

X3, 25 MHz crystal with socket for an STM32F107VC microcontroller, it can be

removed from the socket when an internal RC clock is used.

4.6

Reset source

The reset signal of the STM3210C-EVAL board is low active and the reset sources include:

●

Reset button, B1

●

Debugging tools from JTAG connector CN13 and trace connector CN12

●

Daughterboard from CN9

●

RS-232 connector CN6 for ISP.

Table 3.

Boot related switches

Switch

Boot from

Configuration

SW1 and SW2

STM3210C-EVAL boots from user Flash when SW2 is set as shown on

the right. SW1 setting does not matter in this configuration. (Default)

STM3210C-EVAL boots from system memory when SW1 and SW2 are

set as shown:

STM3210C-EVAL boots from embedded SRAM when SW1 and SW2

are set as shown:

Table 4.

Reset related jumper

Jumper

Description

JP20

Enables reset of the STM32F107VC embedded JTAG TAP controller each

time a system reset occurs. JP20 connects the TRST signal from the JTAG

connection with the system reset signal RESET#.

Default setting: not fitted.

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