AN3422 datasheet(14/52 Pages) STMICROELECTRONICS

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Peripheral migration

AN3422

14/52

Doc ID 018976 Rev 2

4.2

System architecture

The STM32L MCU family, based on the Cortex-M3 core, extends ST’s ultra-low-power

portfolio in performance, features, memory size and package pin count. It combines very

high performance and ultra-low power consumption, through the use of an optimized

architecture and ST’s proprietary ultra-low leakage process, that is also used in the STM8L

family. The STM32L family offers three different product lines (STM32L Medium-density,

STM32L Medium-density+ and STM32L High-density).

4.3

Memory mapping

The peripheral address mapping has been changed in the L1 series vs. F1 series, the main

change concerns the GPIOs which have been moved from the APB bus to the AHB bus to

allow them to operate at maximum speed.

The tables below provide the peripheral address mapping correspondence between L1 and

F1 series.

CEC

Yes

Ethernet

Yes

LCD glass

Yes

COMP

Yes

SYSCFG

Yes

AES

Yes

OPAMP

Yes

Table 3.

STM32 peripheral compatibility analysis F1 versus L1 series (continued)

Peripheral

F1 series

L1 series

Compatibility

Comments

Pinout

SW compatibility

Color key:

= New feature or new architecture (Yes++)

= Same feature, but specification change or enhancement (Yes+)

= Feature not available (NA)

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